The FPGA implementation of DB3 discrete wavelet transform and inverse transform based on lifting algorithm is studied to improve the calculation efficiency of wavelet transform. Based on the introduction of lifting algorithm principle, the calculation process of DB3 wavelet transform and its inverse transform is presented. The hardware implementation architecture of transform is designed. The wavelet coefficient can replace the original signal data in this architecture, which doesn’t need any more memory to store the calculation data. The pipelining technology is used to speedup the calculation and output of wavelet coefficient. The lifting algorithm architecture is simulated in Quartus software and simulation result proves the correctness of the architecture. The traditional DB3 wavelet filter and the lifting algorithm architecture are used to process simulated signal by wavelet threshold de-noising. The results show that the signal noise ratio of method in this thesis is less than the traditional method, while it’s still in a sustainable range and the calculation speed is higher than the traditional method.