In order to solve the problem of low conversion bandwidth of continuous-time D-? (CTD-?) modulators which are widely used in various nuclear signal processing circuits and nuclear detection equipment, an excess loop delay (ELD) quantizer with 1.5 clock cycle is proposed to obtain higher sampling rate, and an excess loop delay compensation based on sample-and-hold is proposed. The effect of 1.5 clock cycle excess loop delay compensation on the signal transfer function of the feedforward structure is analyzed, and a method to improve the signel transfer function (STF) performance of the modulator is proposed. Based on these analyses, a CTD-? modulator architecture is designed, and the circuit level implementation of the main design blocks is given. The simulation results show that the CTD-? modulator can significantly reduce the out-of-band peak of STF, and obtain 31 MHz conversion bandwidth, 72.5 dB signal-to-noise ratio, and 76.3 dB dynamic range, with only 33 mW power consumption at 1.2 V power supply.