An IP core based on SM4 encryption and decryption algorithm is designed to meet the encryption requirements of bus communication between terminal devices and the requirements of convenient transplantation and development of encryption hardware programs. A lightweight single-round loop iteration structure is adopted to reduce the consumption of FPGA logic resources while meeting the throughput requirements, wherein the consumption of a lookup table (LUT) is 2 447, and the consumption of a flip-flop (FF) is 2 914; The independent operation mode of encryption and decryption is adopted, so that the encryption operation and the decryption operation in the communication process can be carried out at the same time without mutual interference; A “linear transformation parameter controllable” mechanism is used to change the encryption security from a single key as a guarantee to a double guarantee of “key + linear transformation parameter”, which improves the security of encryption. The test results show that the IP core can be applied to the data encryption of UART(485/422/232), CAN, 1553B and other buses under the condition of meeting the throughput requirements, and the performance is stable.