In order to improve the bandwidth, flexibility and reliability of inter chip and inter board interconnection, this paper proposes a design method of SRIO (serial rapid IO) endpoint based on field programmable gate array (FPGA). Introduces the application of RapidIO, analyzes the SRIO IP core and its parameter setting, compiles the user logic with the official example provided by Xilinx, and realizes the high-speed communication between FPGA and DSP. The test results show that the design has a high bandwidth and a certain reference value.