In order to improve the performance of digital signal processing circuit, an improved scheme of logic layer Boolean function of 16 bit traditional conditional carry select adder (CCS) is proposed. Verilog language and Synopsys are used to simulate 16 bit modified and traditional conditional carry adders. The results show that the proposed scheme can significantly reduce the critical path delay while reducing the power consumption of the adder, and its performance is significantly better than that of the traditional adder.